Name
Abstract | ||
|---|---|---|
We introduce a new verification methodology for modern micro-processors that uses a simple checker processor to validate the exe-cution of a companion high-performance processor. The checker can be viewed as an at-speed emulator that is formally verified to be compliant to an ISA specification. This verification approach en-ables the practical deployment of formal methods without impact-ing overall performance. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/378239.378265 | DAC |
Keywords | Field | DocType |
instruction sets,computer bugs,boolean functions,formal method,formal verification,out of order,testing,formal methods,degradation | Functional verification,Computer architecture,Software deployment,Computer science,Intelligent verification,Physical verification,Electronic engineering,Verification,Formal methods,Embedded system,Formal verification,Scalability | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-297-2 | 14 |
PageRank | References | Authors |
1.08 | 9 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maher N. Mneimneh | 1 | 212 | 11.34 |
| Fadi A. Aloul | 2 | 351 | 32.74 |
| Christopher T. Weaver | 3 | 14 | 1.08 |
| Saugata Chatterjee | 4 | 61 | 14.20 |
| Karem A. Sakallah | 5 | 3314 | 287.44 |
| Todd Austin | 6 | 6432 | 539.01 |