Title
Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback
Abstract
This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130nm and 90nm. In both cases, the supply voltage is 1.2V. The best LNA designed in 130nm achieves a bandwidth of 2.94GHz with a flat voltage gain (A"v) of 16.5dB and a power consumption of 3.2mW. The same LNA topology designed in 90nm technology has a bandwidth of 11.2GHz, featuring a voltage gain of 16.6dB and consuming 1.9mW. Both LNAs are input-impedance matched and have a noise figure below 2.4dB measured at 2.4GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130nm technology, achieving an area of 0.012mm^2, which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.
Year
DOI
Venue
2012
10.1016/j.mejo.2012.03.014
Microelectronics Journal
Keywords
Field
DocType
low noise amplifier,different cmos technology process,efficient biasing circuit strategy,comparative study,suitable biasing circuit,different biasing circuit,best lna,lna topology,flat voltage gain,lna performance,best-performance lna circuit,case study
Wideband,Low-noise amplifier,Noise figure,Inductor,CMOS,Electronic engineering,Bandwidth (signal processing),Engineering,Electronic circuit,Electrical engineering,Amplifier
Journal
Volume
Issue
ISSN
43
10
0026-2692
Citations 
PageRank 
References 
2
0.39
5
Authors
5