Paper Info
Title
High throughput energy efficient parallel FFT architecture on FPGAs
Abstract
Throughput is a key performance metric for streaming FFT architectures. However, increasing spatial parallelism to improve throughput introduces complex routing, thus resulting in high power consumption. In this paper, we propose a high throughput energy efficient parallel FFT architecture based on Cooley-Tukey algorithm. Multiple pipeline FFT processors using time-multiplexing are utilized to perform FFT computation tasks in parallel. This design realizes high performance using task-level parallelism and avoids complex routing. Furthermore, to reduce the memory power consumption, a periodic memory activation (PMA) scheme is developed. By analyzing energy efficiency (defined as GOPS/Joule) asymptotically, we show that our design achieves a low energy efficiency complexity while satisfying a high-throughput requirement. For N-point FFT (64 ≤ N ≤ 4096), our proposed architecture achieves 50 ~ 63 GOPS/Joule, i.e., up to 78% of the Peak Energy Efficiency of FFT designs on FPGAs. Compared with a state-of-the-art design, our design improves the energy efficiency (defined as GOPS/Joule) by 17% to 26% with the same throughput.
Year
DOI
Venue
2013
10.1109/HPEC.2013.6670343
HPEC
Keywords
DocType
ISSN
power aware computing,periodic memory activation scheme,fast fourier transform,energy conservation,time-multiplexing,task-level parallelism,cooley-tukey algorithm,multiple pipeline fft processors,memory power consumption reduction,high throughput energy efficient parallel fft architecture,pma scheme,fpga,field programmable gate arrays,fast fourier transforms,pipeline processing
Conference
2377-6943
ISBN
Citations 
PageRank 
978-1-4799-1364-0
8
0.62
References 
Authors
9
3
Name
Order
Citations
PageRank
Ren Chen110710.23
Park, N.216016.89
Viktor K. Prasanna37211762.74