Name
Title | ||
|---|---|---|
White-box current source modeling including parameter variation and its application in timing simulation |
Abstract | ||
|---|---|---|
This paper presents a novel method for generating current source models (CSMs) for logic cells that efficiently captures the influences of parameter variation and supply voltage drops. The characterization exploits topological information from the transistor netlist resulting in typically 80x faster CSM library generation. The parametric CSMs have been integrated into a commercial FastSPICE simulator to further accelerate path-based timing analysis with transistor level accuracy. Without loss of accuracy, simulation times were reduced by 4x to 98x. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/978-3-642-17752-1_20 | PATMOS |
Keywords | Field | DocType |
transistor level accuracy,novel method,path-based timing analysis,white-box current source modeling,parametric csms,timing simulation,csm library generation,parameter variation,current source model,commercial fastspice simulator,logic cell,transistor netlist,timing analysis | Netlist,Transistor model,Simulation,Computer science,Current source,White box,Voltage drop,Real-time computing,Electronic engineering,Parametric statistics,Static timing analysis,Transistor | Conference |
Volume | ISSN | ISBN |
6448 | 0302-9743 | 3-642-17751-4 |
Citations | PageRank | References |
2 | 0.40 | 19 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christoph Knoth | 1 | 11 | 2.08 |
| Irina Eichwald | 2 | 2 | 0.40 |
| Petra Nordholz | 3 | 5 | 0.81 |
| Ulf Schlichtmann | 4 | 645 | 70.67 |