Name
Abstract | ||
|---|---|---|
NBTI (Negative Bias Temperature Instability), which can degrade the switching speed of PMOS transistors, has become a major reliability challenge. Meanwhile, reducing leakage consumption has become major design goals. In this paper, we propose a novel transmission gate-based (TG) technique to minimize NBTI-induced degradation and leakage. This technique provides higher flexibility compared to the gate replacement technique. Simulation results show our proposed technique has up to 20X and 2.44X on average improvement on NBTI-induced degradation with comparable leakage power reduction. With a 19% area penalty, combining our technique and the gate replacement can reduce 19.39% of the total leakage power and 36.56% of the NBTI-induced circuit degradation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISLPED.2011.5993625 | ISLPED |
Keywords | Field | DocType |
major design goal,aging,performance degradation,gate replacement,nbti-induced circuit degradation,pmos transistors,total leakage power,proposed technique,transmission gate,tg-based technique,leakage power reduction,leakage reduction,gate replacement technique,semiconductor device reliability,leakage consumption,leakage optimization,reliability,major reliability challenge,nbti degradation,comparable leakage power reduction,nbti,negative bias temperature instability,mosfet,nbti-induced degradation,degradation,logic gates,stress,logic gate | Switching time,Logic gate,Leakage (electronics),Computer science,Electronic engineering,Negative-bias temperature instability,Transmission gate,PMOS logic,MOSFET,Transistor | Conference |
ISSN | ISBN | Citations |
Pending E-ISBN : 978-1-61284-659-0 | 978-1-61284-659-0 | 4 |
PageRank | References | Authors |
0.44 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chin-Hung Lin | 1 | 45 | 4.26 |
| Ing-Chao Lin | 2 | 153 | 15.96 |
| Kuan-Hui Li | 3 | 20 | 1.24 |