Name
Abstract | ||
|---|---|---|
A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with Clock Data Recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured. In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405729 | PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
Keywords | Field | DocType |
transceivers,intersymbol interference,lower bound,intellectual property,bit error rate,synchronisation,programmable logic devices,duty cycle | Transmitter,Intersymbol interference,Transceiver,Pass transistor logic,Computer science,Electronic engineering,CMOS,SerDes,Bit error rate,Programmable logic device | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Simar Maangat | 1 | 0 | 0.34 |
| Toan Nguyen | 2 | 55 | 15.70 |
| Wilson Wong | 3 | 0 | 0.68 |
| Sergey Shumarayev | 4 | 23 | 5.27 |
| Tina Tran | 5 | 0 | 0.34 |
| Tim Hoang | 6 | 1 | 0.69 |
| Richard Cliff | 7 | 144 | 15.27 |