Name
Abstract | ||
|---|---|---|
A new scaled radix-4 CORDIC architecture that incorporates pipelining and parallelism is presented. The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision. A 16 bit radix-4 CORDIC architecture is implemented on the available FPGA platform. The corresponding latency of the architecture is eight clock cycles and throughput rate is one valid result per eight clock cycles. The entire scaled architecture operates at 56.96MHz of clock rate with a power consumption of 380mW. The speed can be enhanced with the upgraded version of FPGA device. A speed-area optimized processor is obtained through this architecture and is suitable for real time applications. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1016/j.micpro.2010.01.002 | Microprocessors and Microsystems - Embedded Hardware Design |
Keywords | Field | DocType |
radix-4 cordic processor,valid result,available fpga platform,throughput rate,corresponding latency,radix-4 cordic architecture,power consumption,fpga device,clock rate,architectural design,fpga implementation,n bit precision,clock cycle,latency,speed,throughput,cordic | Throughput (business),Pipeline (computing),Latency (engineering),Computer science,16-bit,Parallel computing,Field-programmable gate array,Real-time computing,CORDIC,Throughput,Clock rate | Journal |
Volume | Issue | ISSN |
34 | 2-4 | Microprocessors and Microsystems |
Citations | PageRank | References |
3 | 0.46 | 12 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaushik Bhattacharyya | 1 | 13 | 3.55 |
| Rakesh Biswas | 2 | 6 | 2.66 |
| Anindya Sundar Dhar | 3 | 97 | 26.09 |
| Swapna Banerjee | 4 | 196 | 30.07 |