Name
Abstract | ||
|---|---|---|
The CMOS-based IBM S/390 Parallel Enterprise Servers™ have always employed the technique of memory caching to bridge the gap between processor speed and main-memory access time. However, that gap has widened with each succeeding system generation, requiring increasingly sophisticated, multiple-level cache structures in order to minimize memory-access latency. The IBM S/390® G5 and G6 include two-level caching, with a binodal second-level cache. This paper reviews the principles of cache design, discusses the performance requirements of S/390 relative to caching, and describes how those requirements are addressed by the binodal L2 cache in the G5 and G6 systems. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1147/rd.435.0847 | IBM Journal of Research and Development |
Keywords | Field | DocType |
main-memory access time,g6 system,cache design,two-level caching,parallel enterprise servers,multiple-level cache structure,cmos-based ibm,storage hierarchy,g6 performance consideration,memory-access latency,l2 cache,binodal second-level cache | Cache invalidation,Cache pollution,Cache,Computer science,CPU cache,Real-time computing,Cache algorithms,Page cache,Cache coloring,Smart Cache,Operating system | Journal |
Volume | Issue | ISSN |
43 | 5 | 0018-8646 |
Citations | PageRank | References |
5 | 1.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. M. Jackson | 1 | 7 | 1.72 |
| K. N. Langston | 2 | 5 | 1.34 |