Name
Abstract | ||
|---|---|---|
In this paper an asynchronous array multiplier with a new parallel structure is introduced. This parallel array structure is designed to make the computation time faster with lower power consumption. An asymmetric array structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional Booth encoding array structures and that the multiplier with the proposed array structure shows reduction of 40% in the computational time with relatively lower power consumption |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ARVLSI.2001.915561 | ARVLSI |
Keywords | Field | DocType |
computational time,parallel array structure,power consumption,asymmetric parallel array structure,average computation time,parallel architectures,conventional booth encoding array,multiplying circuits,low-power electronics,asymmetric array structure,new parallel structure,computation time,asynchronous array multiplier,asynchronous circuits,lower power consumption,proposed array structure,computational modeling,concurrent computing,low power electronics,digital signal processing,tree data structures,encoding | Array data structure,Asynchronous communication,Booth encoding,Computer science,Parallel computing,Multiplier (economics),Parallel array,Computation,Power consumption,Low-power electronics | Conference |
ISSN | ISBN | Citations |
1522-869X | 0-7695-1038-8 | 3 |
PageRank | References | Authors |
0.62 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chan-ho Park | 1 | 23 | 6.19 |
| Byung-Soo Choi | 2 | 46 | 7.09 |
| Dongik Lee | 3 | 77 | 14.46 |
| Ho-yong Choi | 4 | 7 | 3.00 |