Name
Abstract | ||
|---|---|---|
In general, mapping a circuit onto several chips incurs a physical setting which differs from those within a chip. Specifically, the delay of chip-to-chip interconnections is much longer than on-chip delays of wires and gates. This delay effects the bandwidth as well. In addition, the clock skew between chips is larger than the clock skew within a chip. One may mistakenly conclude that the feasible clock period of a systolic array cannot be smaller than the maximal delay of an interconnection in a realization of the circuit. This paper proposes a technique for mapping large systolic linear arrays and systolic two-dimensional arrays onto several chips while almost maintaining the clock rates which are obtainable when these circuits are small enough to fit into a single chip. Our solution does not rely on special analogue techniques. It is described in a sequence of transformations (logic duplication and retiming), reductions, and an implementation of interconnections which have a required behavior in a given physical setting. It is shown that each step preserves functionality, and subsequently, the correctness of the proposed solution is implied. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1016/S0167-9260(97)00028-X | Integration |
Keywords | DocType | Volume |
physical setting,large systolic linear array,feasible clock period,clock skews,systolic array,delay effect,chip-to-chip delays,clock skew,single chip,clock rate,maximal delay,on-chip delay,chip-to-chip delay,retiming,ambient intelligence,logic design,chip,logic,computer science,very large scale integration,bandwidth | Conference | 24 |
Issue | ISSN | ISBN |
2 | Integration, the VLSI Journal | 0-8186-7542-X |
Citations | PageRank | References |
1 | 0.40 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guy Even | 1 | 1194 | 136.90 |
| Ami Litman | 2 | 240 | 49.78 |