Name
Abstract | ||
|---|---|---|
This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y-access MOS (column-direction access transistor) can improve dummy-read cells' noise margin and isolate the pre-charge noise from bit-lines in synchronous or asynchronous clock operation. The paper also proposes a scheme of combining the row access transistor and sharing bit-line with an adjacent bit-cell. This scheme can reduce the bit-line number to half and mitigate the current consumption of the write/read buffer caused by pre-charging the bit-line to VDD. Furthermore, Y-passgate (column direction access transistor) numbers can also be reduced to half with the proposed DP 10T SRAM architecture. The result shows that write/read buffer current consumption was reduced by over 30%, compared to the conventional DP 8T structure from 1.4 V to 0.6 V VDD. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1166/jolpe.2012.1208 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
10T, Dual-Port, SRAM, Write/Read Disturb | Asynchronous communication,Static noise margin,Bit line,Electronic engineering,CMOS,Static random-access memory,Current consumption,Engineering,Noise margin,Transistor | Journal |
Volume | Issue | ISSN |
8 | 4 | 1546-1998 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dao-Ping Wang | 1 | 5 | 1.32 |
| Wei Hwang | 2 | 254 | 44.40 |