Name
Abstract | ||
|---|---|---|
In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a 0.18µm CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply. The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc (@Fs=20MHz, Fin=1MHz) is measured. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1366110.1366215 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
1-poly 6-metal process,output duty cycle,pipeline analog,cmos device,proposed adc,duty-correction circuit,q channel,duty cycle,input clock duty cycle,pipelined adc,digital converter,prototype adc,cmos,pipeline | Duty,Computer science,Duty cycle,Communication channel,Spurious-free dynamic range,CMOS,Analog-to-digital converter,Electronic engineering,Real-time computing,Miniaturization,Successive approximation ADC | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae Yong Lee | 1 | 97 | 23.87 |
| Sungil Cho | 2 | 0 | 0.34 |
| Kwangsub Yoon | 3 | 0 | 1.35 |