Name
Title | ||
|---|---|---|
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation |
Abstract | ||
|---|---|---|
For a Mb-class embedded memory, asymmetric three-transistor cell (ATC) DRAM has been reported. The memory cell is a non-destructive-read type and the memory array runs at 0.5V, half the voltage of normal peripheral circuits, on a 90nm generic CMOS logic process. A sense amplifier designed for this DRAM is insensitive to input capacitance and can operate with a power supply voltage as low as 0.5V. Through our experiments, we have identified three ways to improve the ATC DRAM. And these improvements enable the sense time to be 6.3ns and refresh power consumption to be 45µW with 0.3V memory array voltage by simulation results. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VLSID.2006.132 | VLSI Design |
Keywords | Field | DocType |
performance measurement,atc dram,memory array voltage,asymmetric three-transistor cell,sense time,sense amplifier,memory cell,asymmetric three-tr,refresh power consumption,memory array operation,power supply voltage,memory array,mb-class embedded memory,amplifiers,logic design | Sense amplifier,Dynamic random-access memory,Semiconductor memory,Computer science,Non-volatile random-access memory,Static random-access memory,Real-time computing,Electronic engineering,Memory controller,Memory refresh,Memory cell | Conference |
ISBN | Citations | PageRank |
0-7695-2502-4 | 0 | 0.34 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Motoi Ichihashi | 1 | 4 | 1.17 |
| Haruki Toda | 2 | 4 | 0.83 |