Name
Title | ||
|---|---|---|
On the optimal four-way switch box routing structures of FPGA greedy routing architectures |
Abstract | ||
|---|---|---|
The problem of mapping a global routing to a detailed routing in a number of 2D routing architectures has been shown to be NP-complete. These routing structures include the Xilinx style routing architecture, as well as architectures with significantly higher switching flexibility. In response to this complexity, a different class of FPGA structures called Greedy Routing Architectures (GRAs), where a locally optimal switch box routing can be greedily extended to an optimal, whole chip routing, was proposed [1-3]. On GRAs, routing of the entire chip can be decomposed into three kinds of four-way switch box routing problems where each can be optimally solved in polynomial time. In this paper, we explore the optimal structures of these four-way switch box routing problems and give the requirement of their minimum routing switches. (C) 1998 Elsevier Science B.V. All rights reserved. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1016/S0167-9260(98)00011-X | Integration |
Keywords | Field | DocType |
optimal four-way switch box,fpga greedy routing architecture | Equal-cost multi-path routing,Link-state routing protocol,Multipath routing,Dynamic Source Routing,Enhanced Interior Gateway Routing Protocol,Computer science,Static routing,Policy-based routing,Real-time computing,Electronic engineering,Zone Routing Protocol | Journal |
Volume | Issue | ISSN |
25 | 2 | 0167-9260 |
Citations | PageRank | References |
10 | 0.90 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiaofeng Pan | 1 | 12 | 1.71 |
| Yu-liang Wu | 2 | 316 | 37.60 |
| C. K. Wong | 3 | 10 | 0.90 |
| Guiying Yan | 4 | 196 | 22.92 |