Name
Abstract | ||
|---|---|---|
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1°C and 11.8°C lower peak temperature on the average, compared to that of the conventional low-power and thermal-aware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1176254.1176285 | CODES+ISSS |
Keywords | Field | DocType |
peak temperature,thermal-aware method,proposed thermal-aware binding algorithm,binding problem,thermal-aware module,network flow method,primary objective,thermal-aware binding problem,new problem,thermal-aware high-level synthesis,secondary objective,chip temperature,high level synthesis,network flow,logic design,modules,temperature,diffusion,chip | Logic synthesis,Flow network,Thermal,Computer science,High-level synthesis,Real-time computing,Chip,Heat equation,Binding problem,Floorplan | Conference |
ISBN | Citations | PageRank |
1-59593-370-0 | 10 | 0.60 |
References | Authors | |
14 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pilok Lim | 1 | 18 | 1.12 |
| Taewhan Kim | 2 | 1087 | 113.31 |