Title
Using GPU to accelerate a pin-based multi-level cache simulator
Abstract
Trace-driven simulation methodology is the most widely used method to evaluate the design of future computer memory architecture. Since this methodology demands large amounts of storage and computer time, there is a growing need for simulation methodologies to determine the memory system requirements of emerging workloads in a reasonable amount of time. Several techniques have been proposed to reduce the space that store memory reference and improve the performance of sequential trace-driven simulation. This paper presents the use of binary instrumentation as the memory reference generator and parallel simulation technique that based on the generic graphics processing unit (GPU). One way to achieve fast parallel simulation is to simulate the independent sets of a cache concurrently on different compute resource, but results show that this method is not efficient because of a high correlation of the activity between different sets. To put parallelism to effective use, we show that a multi-configuration simulation in single pass method gains 2.44x performance improvement compared to traditional sequential algorithm.
Year
DOI
Venue
2010
10.1145/1878537.1878637
SpringSim
Keywords
Field
DocType
trace-driven simulation methodology,store memory reference,future computer memory architecture,parallel simulation technique,pin-based multi-level cache simulator,multi-configuration simulation,memory reference generator,memory system requirement,simulation methodology,parallel simulation,sequential trace-driven simulation,difference set,cache,independent set,gpgpu
Uniform memory access,Cache pollution,Shared memory,Simulation,Computer science,Parallel computing,Non-uniform memory access,Cache coloring,Sequential algorithm,Computer memory,CUDA Pinned memory
Conference
Citations 
PageRank 
References 
2
0.41
10
Authors
4
Name
Order
Citations
PageRank
Han Wan12810.98
Gao Xiaopeng2121.02
Long Xiang3393.51
Chen Xianqin420.41