Title
Déjà Vu Switching for Multiplane NoCs
Abstract
In chip-multiprocessors (CMPs) the network-on-chip (NoC) carries cache coherence and data messages. These messages may be classified into critical and non-critical messages. Hence, instead of having one interconnect plane to serve all traffic, power can be saved if the NoC is split into two planes: a fast plane dedicated to the critical messages and a slower, more power-efficient plane dedicated only to the non-critical messages. This split, however, can be beneficial to save energy only if system performance is not significantly degraded by the slower plane. In this work we first motivate the need for a timely delivery of the "non-critical" messages. Second, we propose Déjà Vu switching, a simple algorithm that enables reducing the voltage and frequency of one plane while reducing communication latency through circuit switching and support of advance, possibly conflicting, circuit reservations. Finally, we study the constraints that govern how slow the power-efficient plane can operate without negatively impacting system performance. We evaluate our design through simulations of 16 and 64 core CMPs. The results show that we can achieve an average NoC energy savings of 43% and 53%, respectively.
Year
DOI
Venue
2012
10.1109/NOCS.2012.9
NOCS
Keywords
Field
DocType
slower plane,fast plane,vu switching,circuit reservation,average noc energy saving,non-critical message,impacting system performance,core cmps,power-efficient plane,critical message,multiplane nocs,switches,routing,system performance,circuit switching,network on chip,coherence,noc
Latency (engineering),Computer science,Computer network,Real-time computing,Déjà vu,Circuit switching,Voltage,Parallel computing,Network on a chip,SIMPLE algorithm,Interconnection,Embedded system,Cache coherence
Conference
Citations 
PageRank 
References 
18
0.68
18
Authors
3
Name
Order
Citations
PageRank
Ahmed K. Abousamra1231.51
Rami G. Melhem217421.11
Alex K. Jones357861.61