Name
Abstract | ||
|---|---|---|
BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1007/BF00133501 | J. Electronic Testing |
Keywords | Field | DocType |
Built-in self-test,design for testability,knowledge-based expert system,pseudorandom testing | Design for testing,Iterative and incremental development,Computer science,Expert system,Electronic engineering,Combinational logic,Prolog,VHDL,Pseudorandom number generator,Built-in self-test | Journal |
Volume | Issue | Citations |
2 | 2 | 4 |
PageRank | References | Authors |
0.77 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kwang-Hyun Kim | 1 | 18 | 4.28 |
| joseph g tront | 2 | 149 | 24.97 |
| Dong S. Ha | 3 | 133 | 14.49 |