Paper Info
Title
Implementation of low power adder design and analysis based on power reduction technique
Abstract
This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier. Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design. The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.
Year
DOI
Venue
2008
10.1016/j.mejo.2008.07.002
Microelectronics Journal
Keywords
Field
DocType
low leakage power,low power adder design,low power adder,essential part,proposed technique offer power,power reduction technique,cmos digital circuit,high performance circuit design,proposed design,conventional design,fault coverage,digital circuits,circuit design
Fault coverage,Adder,Circuit design,Electronic engineering,Multiplier (economics),CMOS,Power electronics,Engineering,Integrated circuit,Low-power electronics
Journal
Volume
Issue
ISSN
39
12
Microelectronics Journal
Citations 
PageRank 
References 
1
0.39
12
Authors
1
Name
Order
Citations
PageRank
Taikyeong T. Jeong11612.16