Title
A tightly coupled accelerator infrastructure for exact arithmetics
Abstract
Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In this domain, however, the problem of accuracy arises due to rounding of intermediate results. One solution is to avoid intermediate rounding by using exact arithmetic. The use of FPGAs as application-specific accelerators can speed up such operations compared to their software implementation. In this paper, we present a system approach employing state-of-the art FPGA and interconnection technology for exact arithmetic with double-precision operands, delivering up to 400M exact MACs/s in total and providing a speedup of up to 88 times over competing software implementations in the case of matrix multiplication.
Year
DOI
Venue
2010
10.1007/978-3-642-11950-7_20
ARCS
Keywords
Field
DocType
exact arithmetics,exact arithmetic,software implementation,accelerator infrastructure,double-precision operands,application-specific accelerator,intermediate rounding,available computing power,processor speed,intermediate result,exact macs,complex problem,matrix multiplication,numerical simulation
Computer science,Operand,Parallel computing,Field-programmable gate array,Arithmetic,Real-time computing,Rounding,Interconnection,Matrix multiplication,Clock rate,Speedup,Computation
Conference
Volume
ISSN
ISBN
5974
0302-9743
3-642-11949-2
Citations 
PageRank 
References 
0
0.34
9
Authors
2
Name
Order
Citations
PageRank
Fabian Nowak1396.52
Rainer Buchty214318.44