Name
Abstract | ||
|---|---|---|
This paper presents an extensive analysis of transistor sizing for via-configurable regular fabrics. Different design aspects have been considered such as transistor stacking, logic gate drive strength options and critical delay paths. Performance degradation due to the use of transistor regular layout (TRL) is expected in comparison to standard cells, as a consequence of the loss in design flexibility. In this work, the speed and power consumption impact is evaluated when addressing such lithography-aware regular fabrics in digital integrated circuit design. Experimental results were obtained at the transistor level through electrical simulations, taking into account the predictive PTM 45nm CMOS parameters. The analysis presented herein can be easily extended to other technology nodes and fabrication processes. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2020876.2020900 | SBCCI |
Keywords | Field | DocType |
digital integrated circuit design,design flexibility,cmos parameter,different design aspect,transistor regular layout,extensive analysis,via-configurable regular fabric,lithography-aware regular fabric,transistor level,transistor sizing,logic gate,digital design,integrated circuit | Logic gate,Computer science,Electronic engineering,Full custom,CMOS,Transistor sizing,Lithography,Transistor,Integrated circuit,Electrical engineering,Fabrication | Conference |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Felipe dos Santos Marranghello | 1 | 0 | 0.34 |
| Vinicius Dal Bem | 2 | 7 | 1.00 |
| André Inácio Reis | 3 | 134 | 21.33 |
| Francesc Moll | 4 | 55 | 14.87 |
| Renato Perez Ribas | 5 | 59 | 6.32 |