Paper Info
Title
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)
Abstract
Despite their many advantages, FPGAs are still inefficient. This inefficiency is mainly due to programmable routing networks; however, FPGA logic blocks also have their share of contribution. From the performance perspective, fewer hops in the routing network translates to a shorter critical path; and that requires large logic blocks capable of covering big portions of circuits. Recent work has shown that And-Inverter Cones (AICs) can considerably reduce the number of logic block levels compared to Look-Up Tables (LUTs). The best performance is achieved when both AICs and LUTs are used, but the AIC implementation requires radical changes in the FPGAs architecture. In this paper, we use AICs as shadow logic for LUTs in LUT-clusters, which requires minimal architectural changes while exploiting the benefits of both AICs and LUTs. The basic idea is to reuse the input crossbar of LUT-clusters for the shadow AICs while combining both LUTs and AICs in the same cluster. We also propose changes in the AIC architecture to enhance mapping on AICs. Our experimental results indicate that the new cluster architecture can reduce the average circuit delay by 12% with respect to standard FPGA clusters. However, this performance gain comes at a price of 43% area overhead in terms of number of logic clusters. Our results show that for a modest 6% increase in area, FPGA manufacturers can move towards next-generation FPGA logic elements. This transition would provide faster design options without major architectural changes.
Year
DOI
Venue
2013
10.1145/2435264.2435348
FPGA
Keywords
Field
DocType
fpga manufacturer,large logic block,shadow logic,aic architecture,standard fpga cluster,next-generation fpga logic element,logic block level,minimal architectural impact,shadow aics,and-inverter cone,logic cluster,fpga logic block
Inverter,Architecture,Computer science,Reuse,Parallel computing,Field-programmable gate array,Real-time computing,Logic block,Critical path method,Electronic circuit,Crossbar switch
Conference
Citations 
PageRank 
References 
3
0.43
0
Authors
5
Name
Order
Citations
PageRank
Hadi Parandeh-Afshar113412.24
Grace Zgheib2216.40
David Novo317712.58
Madhura Purnaprajna4476.34
Paolo Ienne52246199.26