Name
Abstract | ||
|---|---|---|
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm(2) in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays and processing elements is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CICC.2009.5280875 | PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
Keywords | Field | DocType |
cmos integrated circuits,digital circuits,chip,cmos technology,emulation,noise,low power electronics,time series | Digital electronics,Parasitic capacitance,Computer science,Waveform,Electronic engineering,Image noise,CMOS,Emulation,Noise generator,Electrical engineering,Low-power electronics | Conference |
Citations | PageRank | References |
1 | 0.38 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tetsuro Matsuno | 1 | 26 | 4.50 |
| Daisuke Fujimoto | 2 | 25 | 6.52 |
| Daisuke Kosaka | 3 | 20 | 3.98 |
| Naoyuki Hamanishi | 4 | 14 | 8.16 |
| Ken Tanabe | 5 | 1 | 0.72 |
| Masazumi Shiochi | 6 | 1 | 0.72 |
| Makoto Nagata | 7 | 285 | 76.47 |