Name
Abstract | ||
|---|---|---|
In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5117957 | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
Keywords | Field | DocType |
data mining,quantization,computer architecture,propagation delay,cmos integrated circuits,cmos technology,voltage | FO4,Propagation delay,Computer science,CMOS,Electronic engineering,Analog-to-digital converter,Electronic circuit,Quantization (signal processing),Energy consumption,Scalability | Conference |
Citations | PageRank | References |
2 | 0.42 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yahya M. Tousi | 1 | 161 | 13.68 |
| Guansheng Li | 2 | 97 | 7.48 |
| Arjang Hassibi | 3 | 122 | 25.61 |
| Ehsan Afshari | 4 | 325 | 36.65 |