Name
Abstract | ||
|---|---|---|
This work describes a novel approach to FPGA placement. Most conventional FPGA CAD flow clusters circuits into CLBs prior to placing it. We show that is it possible to achieve 28% and 21% improvement in wirelength and minimum channel width respectively, while suffering only 1.8% in critical path delay by placing individual LUTs directly. By utilizing a good parallel placer, the novel approach can achieve speedups over the conventional uni-processor placers as well. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2145694.2145754 | FPGA |
Keywords | Field | DocType |
conventional fpga cad flow,novel approach,conventional uni-processor placers,minimum channel width,clusters circuit,individual lut placement,good parallel placer,critical path delay,individual luts,parallel fpga placement,fpga placement,critical path,fpga | Lookup table,Computer science,Parallel computing,Field-programmable gate array,Critical path delay,Channel width,Real-time computing,Electronic circuit,Cad flow | Conference |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chris C. Wang | 1 | 10 | 1.13 |
| Guy G.F. Lemieux | 2 | 53 | 5.06 |