Name
Abstract | ||
|---|---|---|
A scalable backplane topology which allows a practically unlimited number of modules with identical interfaces is presented. Short, buffered, point-to-point connections overcome clock skew problems. Synchronized, pipelined data transfer operations ensure high throughput and reasonably low latency times for fine-grain parallel algorithms. A simple bus interface logic without any special hardware configuration guarantees a cheap implementation with standard FPGAs. The measured performance in our FPGA based prototype with 32 bit wide data bus shows a throughput of 160 Mbytes/s for each module with 75 ns latency time between modules. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1016/S1383-7621(00)00002-3 | Journal of Systems Architecture |
Keywords | Field | DocType |
Backplane bus,Scalable multiprocessor implementation,Point-to-point communication bus,Chain bus | 32-bit,Backplane,Parallel algorithm,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Clock skew,Throughput,Latency (engineering),System bus,Embedded system | Journal |
Volume | Issue | ISSN |
46 | 11 | 1383-7621 |
Citations | PageRank | References |
0 | 0.34 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pasi Kolinummi | 1 | 10 | 3.36 |
| Timo Hämäläinen | 2 | 1603 | 194.30 |
| Jukka Saarinen | 3 | 264 | 46.21 |