Title
A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses
Abstract
This paper presents a built-in self-test (BIST) scheme for testing ADCýs static parameters that include Offset Error, Gain Error, Integral Non-linearity (INL) and Differential Non-linearity (DNL). The main components in the scheme contain Control Circuit, Differential Integrator and Test Response Analyzer (TRA). A system clock pulse is used to trig a counter and inputted to Control Circuit that regulates the frequency, duty cycle and amplitude of the system clock pulse to output a regulated clock signal (RLK). The RLK is integrated by the Integrator to become a called step-ramp stimulus. The correct synchronization between the step-ramp stimulus and the counter output codes is achieved. Then the digital TRA can be designed by analyzing the ADCýs output codes and the references of the counterýs output codes. With the integration of gradually increasing duty cycles of the RLK to compensate the nonlinear leakage currents depending on the increasing voltages of the Integrator, the high accurate step-ramp stimulus is generated. Simulation results show that the accuracies of all step-ramp pieces of the stimulus are within 0.5% LSB.
Year
DOI
Venue
2005
10.1109/VTS.2005.6
VTS
Keywords
Field
DocType
counter output code,output code,digital response analyses,testing analog-to-digital converters,high accurate step-ramp stimulus,control circuit,step-ramp stimulus,duty cycle,bist scheme,differential integrator,step-ramp piece,regulated clock signal,system clock pulse,differential nonlinearity,control systems,clock pulse,integral nonlinearity,synchronisation,leakage current,differential non linearity
Clock signal,Integral nonlinearity,Synchronization,Differential nonlinearity,Computer science,Duty cycle,Control theory,Integrator,Electronic engineering,Control system,Built-in self-test
Conference
ISSN
ISBN
Citations 
1093-0167
0-7695-2314-5
9
PageRank 
References 
Authors
0.97
3
1
Name
Order
Citations
PageRank
Yun-Che Wen1293.52