Paper Info
Title
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority
Abstract
This paper presents a low-power coordinate rotation digital computer (CORDIC)-based reconfigurable discrete cosine transform (DCT) architecture. The main idea of this paper is based on the interesting fact that all the computations in DCT are not equally important in generating the frequency domain outputs. Considering the importance difference in the DCT coefficients, the number of CORDIC iterations can be dynamically changed to efficiently tradeoff image quality for power consumption. Thus, the computational energy can be significantly reduced without seriously compromising the image quality. The proposed CORDIC-based 2-D DCT architecture is implemented using 0.13 μm CMOS process, and the experimental results show that our reconfigurable DCT achieves power savings ranging from 22.9% to 52.2% over the CORDIC-based Loeffler DCT at the cost of minor image quality degradations.
Year
DOI
Venue
2014
10.1109/TVLSI.2013.2263232
IEEE Transactions on Very Large Scale Integration Systems
Keywords
Field
DocType
low-power coordinate rotation digital computer,signal processing,low-power,reconfigurable cordic-based low-power dct architecture,low-power electronics,digital arithmetic,image quality degradations,discrete cosine transforms,reconfigurable discrete cosine transform architecture,discrete cosine transform (dct),power savings,data priority,reconfigurable architecture,coordinate rotation digital computer (cordic),cmos digital integrated circuits,size 0.13 mum,cmos,reconfigurable architecture.,low power electronics
Frequency domain,Signal processing,Computer science,Discrete cosine transform,Image quality,Electronic engineering,CORDIC,Ranging,Rotation (mathematics),Low-power electronics
Journal
Volume
Issue
ISSN
22
5
1063-8210
Citations 
PageRank 
References 
8
0.53
15
Authors
3
Name
Order
Citations
PageRank
Min-Woo Lee1378.23
Ji-Hwan Yoon2201.98
Jongsun Park332350.88