Name
Title | ||
|---|---|---|
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect |
Abstract | ||
|---|---|---|
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this paper, we propose a flush delay technique for measuring both regional delay variations and SOI history effect and validate the method using a test structure fabricated in a 65 nm SOI process. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2024724.2024848 | Design Automation Conference |
Keywords | Field | DocType |
flush delay technique,detrimental effect,die-to-die delay variation,soi history effect,nm soi process,soi history effect increase,actual product,regional delay variation,characterizing within-die,delay variation,mitigation technique,die-to-die process variation,logic gates,helium,silicon on insulator,design for manufacturability,logic gate,semiconductor devices,design for manufacture,process variation,history | Silicon on insulator,Logic gate,Computer science,Real-time computing,Electronic engineering,Design for manufacturability,Test structure | Conference |
ISSN | ISBN | Citations |
0738-100x | 978-1-4503-0636-2 | 2 |
PageRank | References | Authors |
0.46 | 2 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jim Aarestad | 1 | 19 | 2.25 |
| Charles Lamech | 2 | 28 | 2.27 |
| Jim Plusquellic | 3 | 546 | 53.16 |
| Dhruva Acharyya | 4 | 82 | 8.56 |
| Kanak B. Agarwal | 5 | 328 | 28.02 |