Name
Abstract | ||
|---|---|---|
This paper presents two fast and accurate methods to estimate the lower bound of supply voltage scaling for standby SRAM/cache leakage power reduction of an SRAM array. The data retention voltage (DRV) defines the minimum supply voltage for a cell to hold its state. Within-die variation causes a statistical distribution of DRV for individual cells in a memory array, and cells far out the tail (i.e. >6sigma) limit the array DRV for large memories. We present two statistical methods to estimate the tail of the DRV distribution. First, we develop a new statistical model based on the connection between DRV and static noise margin (SNM). Second, we apply our Statistical Blockade tool to obtain fast Monte-Carlo simulation and a generalized Pareto distribution (GPD) model for comparison. Both the new model and the GPD model offer a high accuracy (<2% error) and a huge speed-up (>104times for 1 G-b memory) over Monte-Carlo simulation. In addition, both models show a very close agreement with each other at the tail even beyond 7sigma. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ESSCIRC.2007.4430327 | Munich |
Keywords | DocType | ISSN |
statistical methods,statistical blockade tool,cache storage,data retention voltage,statistical distribution,sram array,pareto distribution,cache leakage power reduction,sram chips,memory array,monte-carlo simulation,within-die variation,standby sram,static noise margin,monte carlo methods,generalized pareto distribution model,minimum standby supply voltage,statistical model,monte carlo simulation,lower bound,generalized pareto distribution | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-1125-2 | 21 | 1.70 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| JiaJing Wang | 1 | 205 | 18.24 |
| Amith Singhee | 2 | 347 | 22.94 |
| Rob A. Rutenbar | 3 | 2283 | 280.48 |
| Benton H. Calhoun | 4 | 1396 | 152.14 |