Name
Title | ||
|---|---|---|
Memory and computation efficient hardware design for a 3 spatial and temporal layers SVC encoder |
Abstract | ||
|---|---|---|
Spatial and temporal scalability in Scalable Video Coding (SVC) compression enables a video encoder to generate bit streams efficiently for various resolutions and frame rates. However, doing this requires more complex computations and greater memory bandwidth than H.264/AVC compression. In this paper, the performance and memory bandwidth for a SVC hardware encoder with three spatial and temporal layers are analyzed. Based on the analysis, a novel method is proposed for the source and interlayer data load. Experimental results show that the memory bandwidth is reduced by 77%. Furthermore, the memory access latency of the source data for the base layer is reduced by creating a data load for the base layer overlap with the execution of the enhancement layer. To satisfy the latency requirement, a mode pre-decision algorithm for a hardware SVC encoder is proposed. It reduces the computation of the fractional motion estimation (FME) and the inter-layer residual prediction by 80%. Simulation results show that the proposed methods decrease the BD-PSNR by 0.05 dB and increase the BD-BR by 1.64%, an amount that can be considered negligible in terms of degradation, while an encoding speed of 30 fps for Full HD (1920×1080) videos is achieved at an operating clock frequency of less than 200 MHz1. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TCE.2011.6131172 | IEEE Trans. Consumer Electronics |
Keywords | Field | DocType |
temporal layer svc hardware encoder,memory design,high definition video,h.264-avc compression,memory,audio coding,multi-layer,full hd video,efficient,spatial layer svc hardware encoder,image resolution,storage management,computation,data compression,temporal scalability,interlayer data load,motion estimation,scalable video coding,fractional motion estimation,bd-psnr,operating clock frequency,svc encoder,video coding,enhancement layer,computation efficient hardware design,bit stream,video encoder,memory access latency,memory bandwidth,spatial scalability,hardware,image enhancement,error statistics,predecision algorithm,interlayer residual prediction,satisfiability,static var compensator,bandwidth,scalability,encoding,pipelines,memory management | High-definition video,Memory bandwidth,Computer science,Real-time computing,Memory management,Encoder,Data compression,Computer hardware,Clock rate,Scalable Video Coding,Encoding (memory) | Journal |
Volume | Issue | ISSN |
57 | 4 | 0098-3063 |
Citations | PageRank | References |
2 | 0.39 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyujoong Lee | 1 | 43 | 5.06 |
| Chae-Eun Rhee | 2 | 93 | 11.14 |
| Hyuk-Jae Lee | 3 | 337 | 55.29 |
| Jung Won Kang | 4 | 166 | 12.60 |