Name
Abstract | ||
|---|---|---|
The performance of the instruction memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable instruction memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed in- struction memory hierarchy consists of an instruction cache and a scratchpad memory (SPM). We propose an algorithm to manage this instruction mem- ory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the instruction cache to best suit the application. It an- alyzes the application, partitions the available storage re- sources into SPM and cache, and assigns instructions to them. Our algorithm aims to reduce the instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable instruction mem- ory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the Medi- aBench and the MiBench suites show that our proposed ar- chitecture provides significant performance improvements and energy reduction. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/FPL.2005.1515691 | FPL |
Keywords | Field | DocType |
field programmable gate arrays,embedded systems,instruction sets,embedded system,chip,system performance | Computer architecture,Cache-oblivious algorithm,Memory hierarchy,Cache pollution,Computer science,Instruction set,Scratchpad memory,Parallel computing,Cache-only memory architecture,Memory management,Memory map,Embedded system | Conference |
Citations | PageRank | References |
5 | 0.59 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiguo Ge | 1 | 16 | 2.24 |
| Hock-Beng Lim | 2 | 61 | 8.55 |
| Weng-fai Wong | 3 | 1019 | 83.39 |