Name
Title | ||
|---|---|---|
A 4-Bits CSA Adder Using the Arithmetic A2 Redundant Binary Representation for Mixed Neural Networks with On-Chip Learning |
Abstract | ||
|---|---|---|
This paper presents a time-efficient 4-bits carry select adder (CSA) using the arithmetic A2 redundant binary representation. This structure is very suitable for implementation in VLSI of simple mixed-signal neural networks with on-chip learning. This adder is based on a classical weighted binary carry-select adder with two input/output trans-coders. Comparisons with another FPGA-based A2 adder show that the proposed CMOS structure offers a significant increase in speed, while consuming a little more area. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/CISIM.2008.18 | Ostrava |
Keywords | Field | DocType |
4-bits csa adder,simple mixed-signal neural network,mixed neural networks,select adder,on-chip learning,arithmetic a2 redundant binary,classical weighted binary carry-select,proposed cmos structure,output trans-coders,significant increase,a2 adder show,time-efficient 4-bits,adders,artificial neural networks,input output,network on a chip,circuits,chip,neural networks,computer networks,fpga,system on a chip,redundancy,simulation,very large scale integration,field programmable gate arrays,neural network,vlsi | Adder,Computer science,Arithmetic,Carry-select adder,Serial binary adder,Carry-save adder,Artificial neural network,Very-large-scale integration,Redundant binary representation,Binary number | Conference |
ISBN | Citations | PageRank |
978-0-7695-3184-7 | 0 | 0.34 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hatem Boukadida | 1 | 0 | 0.34 |
| Zied Gafsi | 2 | 0 | 0.34 |
| Néjib Hassen | 3 | 15 | 5.28 |
| Kamel Besbes | 4 | 44 | 15.41 |