Title
Efficient Low Power/Low Swing Bus Design Architectures
Abstract
Novel low-power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re-pull up the low swing voltage to full swing, innovated high-speed, cross-coupled latch voltage receiver circuits are proposed, In applications having high load capacitance due to long interconnections, novel repeater circuits, based also on low swing voltage technique, are introduced. The difference between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.
Year
DOI
Venue
2001
10.1155/2001/63230
VLSI DESIGN
Keywords
Field
DocType
low power design technique,low swing voltage technique,low power bus architecture,long interconnection,repeater circuit
NMOS logic,Computer science,Real-time computing,Electronic engineering,CMOS,PMOS logic,MOSFET,Transistor,Threshold voltage,High impedance,Swing
Journal
Volume
Issue
ISSN
12
3
1065-514X
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Abdoul Rjoub145.84
Odysseas Koufopavlou28915.92