Abstract | ||
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Rapid advances in integrated circuit (IC) development predicted by Moore's Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries employed at untrusted locations can insert malicious Trojan circuits capable of launching attacks in hardware or supporting software-based attacks. In this paper, we provide a method for detecting Trojan circuit denial-of-service attacks using a simple, verifiable hardware guard external to the complex CPU. The operating system produces liveness checks, embedded in the software clock, to which the guard can respond. We also present a novel method for the OS to detect a hardware-software (HW/SW) Trojan privilege escalation attack by using OS-generated checks to test if the CPU hardware is enforcing memory protection (MP). Our implementation of fine-grained periodic checking of MP enforcement incurs only 2.2% overhead using SPECint 2006. |
Year | DOI | Venue |
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2009 | 10.1109/HST.2009.5224959 | Francisco, CA |
Keywords | Field | DocType |
os support,novel method,verifiable hardware guard,malicious trojan circuit,trojan circuit denial-of-service attack,cpu hardware,mp enforcement,complex cpu,ic design,trojan circuit attack,integrated circuit,trojan privilege escalation attack,operating systems,hardware,embedded software,linux,central processing unit,kernel,moore s law,circuits,integrated circuit development,memory protection,testing,security,moore law,integrated circuits,integrated circuit design | Memory protection,Central processing unit,Embedded software,Privilege escalation,Computer science,Real-time computing,Integrated circuit design,SPECint,Integrated circuit development,Trojan,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-4804-3 | 19 | 1.55 |
References | Authors | |
11 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Gedare Bloom | 1 | 68 | 13.95 |
Bhagirath Narahari | 2 | 331 | 42.59 |
Rahul Simha | 3 | 137 | 12.42 |