Name
Title | ||
|---|---|---|
A fast hierarchical arbitration scheme for multi-tb-s packet switches with shared memory switching |
Abstract | ||
|---|---|---|
One challenge in multi-terabit per second packet switches is the design of low latency and high performance arbitration schemes. In this regard, we propose a hierarchical multi-cell arbiter, which interconnects multiple parallel processing devices. By comparison with iterative non-hierarchical multi-cell arbiters, we show that our scheme significantly decreases the signaling overhead and arbitration processing time. Performance evaluation results show the proposed solution maximizes the switch throughput and delay performance. © 2009 Alcatel-Lucent. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1002/bltj.v14:2 | Bell Labs Technical Journal |
Keywords | DocType | Volume |
shared memory | Journal | 14 |
Issue | ISSN | Citations |
2 | 1089-7089 | 0 |
PageRank | References | Authors |
0.34 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Popa | 1 | 14 | 4.10 |
| Georg Post | 2 | 10 | 2.13 |
| Ludovic Noirie | 3 | 61 | 9.20 |