Name
Title | ||
|---|---|---|
SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers |
Abstract | ||
|---|---|---|
In this paper we present SOC-NLNA, a systematic synthesis methodology for fully integrated narrow-band CMOS Low Noise Amplifiers (LNA) in high performance System-on-Chip (SoC) designs. SOC-NLNA is based on deterministic numerical nonlinear optimization and the Normal Boundary Intersection (NBI) method for Pareto optimization. To enable SoC integration, we simultaneously optimize both devices and passive components to yield integrated inductor values that are significantly less than those generated by traditional design techniques. When the synthesized LNAs are simulated using Cadence SpectreRF, SOC-NLNA yields up to 35 and 58 percent improvement in noise figure and gain. Leveraging the efficiency of our methodology, we are able to generate the Pareto surfaces between LNA performance metrics in seconds. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1146909.1147133 | DAC |
Keywords | DocType | ISSN |
narrow-band cmos low noise,systematic synthesis methodology,cadence spectrerf,soc integration,soc-nlna yield,pareto surface,pareto optimization,normal boundary intersection,high performance,lna performance metrics,deterministic numerical nonlinear optimization,nonlinear optimization,integrated circuit design,system on chip,design,low noise amplifier,algorithms,noise figure | Conference | 0738-100X |
ISBN | Citations | PageRank |
1-59593-381-6 | 11 | 0.93 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arthur Nieuwoudt | 1 | 207 | 20.59 |
| Tamer Ragheb | 2 | 266 | 18.65 |
| Yehia Massoud | 3 | 772 | 113.05 |