Name
Abstract | ||
|---|---|---|
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/503048.503050 | FPGA |
Keywords | Field | DocType |
high-level design,background research,performance-driven application,prototype device,architecture,programmable logic,pld architecture,benchmarking experiment,interconnect,high-speed pld architecture,programmable logic device architecture,full design system,architectural decision,fpga,programmable logic device,system performance | Computer architecture,Applications architecture,Complex programmable logic device,Computer science,Programmable Array Logic,Programmable logic array,Simple programmable logic device,Parallel computing,Logic family,Macrocell array,Embedded system,Programmable logic device | Conference |
ISBN | Citations | PageRank |
1-58113-452-5 | 11 | 2.44 |
References | Authors | |
12 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael Hutton | 1 | 11 | 2.44 |
| Vinson Chan | 2 | 11 | 2.44 |
| Peter Kazarian | 3 | 11 | 2.44 |
| Victor Maruri | 4 | 12 | 2.96 |
| Tony Ngai | 5 | 11 | 2.44 |
| Jim Park | 6 | 11 | 2.44 |
| Rakesh H. Patel | 7 | 20 | 5.21 |
| Bruce Pedersen | 8 | 180 | 20.43 |
| Jay Schleicher | 9 | 141 | 15.54 |
| Sergey Shumarayev | 10 | 23 | 5.27 |