Name
Abstract | ||
|---|---|---|
We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server - Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/DATE.1998.655876 | DATE |
Keywords | Field | DocType |
high-performance cmos processor chipset,parallel enterprise server,timing analysis,optimization methodology,static timing analysis,optimization scheme,mathematics,testing,logic,high level synthesis | IBM,Computer architecture,Computer science,High-level synthesis,CMOS,Cmos process,Real-time computing,Static timing analysis,Chipset | Conference |
ISBN | Citations | PageRank |
0-8186-8359-7 | 5 | 1.57 |
References | Authors | |
10 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| U. Fassnacht | 1 | 5 | 1.57 |
| J. Schietke | 2 | 45 | 4.45 |