Paper Info
Title
Hardware/software co-design of a fuzzy RISC processor
Abstract
In this paper, we show how hardware/software co-evaluation can be applied to instruction set definition. As a case study, we show the definition and evaluation of instruction set extensions for fuzzy processing. These instructions are based on the use of subword parallelism to fully exploit the processor's resources by processing multiple data streams in parallel. The proposed instructions are evaluated in software and hardware to gain a balanced view of the costs and benefits of each instruction. We have found that a simple instruction optimized to perform fuzzy rule evaluation offers the most benefit to improve fuzzy processing performance. The instruction set extensions are added to a RISC processor core based on the MIPS instruction set architecture. The core has been described in VHDL so that hardware implementations can be generated using logic synthesis.
Year
DOI
Venue
1998
10.1109/DATE.1998.655961
DATE
Keywords
Field
DocType
fuzzy processing,instruction set extension,software co-design,proposed instruction,fuzzy rule evaluation,fuzzy processing performance,instruction set definition,fuzzy risc processor,mips instruction set architecture,hardware implementation,risc processor core,simple instruction,fuzzy logic,instruction sets,instruction set architecture,costs and benefits,fuzzy sets,logic synthesis,computer architecture,cad,high level synthesis,application specific instruction set processor,vhdl,software metrics,hardware,reduced instruction set computing,processor core
Computer architecture,Application-specific instruction-set processor,Central processing unit,Instruction set,Computer science,Parallel computing,Classic RISC pipeline,Real-time computing,Reduced instruction set computing,Orthogonal instruction set,Control unit,Minimal instruction set computer
Conference
ISBN
Citations 
PageRank 
0-8186-8359-7
6
0.70
References 
Authors
7
2
Name
Order
Citations
PageRank
V. Salapura113516.42
M. Gschwind260.70