Name
Abstract | ||
|---|---|---|
Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without "heroic" compiling techniques, most such processors fall far short of their performan... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/5.964443 | Proceedings of the IEEE |
Keywords | DocType | Volume |
Processor scheduling,VLIW,Pipeline processing,Microcomputers,Workstations,Computer architecture,History,Modems,Shape,Automata | Journal | 89 |
Issue | ISSN | Citations |
11 | 0018-9219 | 27 |
PageRank | References | Authors |
1.22 | 36 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Faraboschi | 1 | 91 | 14.82 |
| joseph a fisher | 2 | 1410 | 264.50 |
| C. Young | 3 | 27 | 1.22 |