Paper Info
Title
Verification of a Data Synchronization Circuit For All Time
Abstract
This paper presents a model and automated proof for a synchronizer circuit that is commonly used to reliably transfer data across clock domains. In contrast with previous work, this paper describes a proof that is valid for all clock rates and phases meeting modest constraints. Furthermore, the proof was realized with an existing model checker - SAL
Year
DOI
Venue
2006
10.1109/ACSD.2006.35
Turku
Keywords
Field
DocType
throughput analysis,application mapping,embedded data flow application,synchronous data flow graphs,useful tool,multiprocessing context,data synchronization circuit,single processor,logic design,transmitters,protocols,circuit analysis,synchronisation,logic circuits,synchronization,formal verification
Logic synthesis,Synchronization,Computer science,Synchronizer,Data synchronization,Real-time computing,Clock synchronization,Synchronous circuit,Asynchronous circuit,Formal verification
Conference
ISSN
ISBN
Citations 
1550-4808
0-7695-2556-3
0
PageRank 
References 
Authors
0.34
6
1
Name
Order
Citations
PageRank
Geoffrey M. Brown122536.38