Paper Info
Title
Bandwidth constrained coordinated HW/SW prefetching for multicores
Abstract
Prefetching is a highly effective latency hiding technique that can greatly improve application performance. However, aggressive prefetching can potentially stress the off-chip bandwidth. The resulting bandwidth stalls can potentially negate the performance gain due to prefetching. In this paper, focusing on a multicore environment, we first study the comparative benefits of hardware and software prefetching and analyze if the two are complimentary or redundant. This analysis also evaluates different aggressiveness levels of hardware prefetching. Secondly, we weigh the positive performance benefits of prefetching against the negative performance effects of bandwidth stalls. Thirdly, we propose a hierarchical prefetch management scheme for multicores that controls the prefetch levels such that the overall performance gain is improved. Lastly, we show that our proposed off-chip bandwidth aware prefetch management scheme is very effective in practice, leading to performance gains of upto about 10% in system throughput over a bandwidth agnostic prefetching scheme.
Year
DOI
Venue
2011
10.1007/978-3-642-23400-2_29
Euro-Par (1)
Keywords
Field
DocType
positive performance benefit,software prefetching,aggressive prefetching,negative performance effect,hardware prefetching,bandwidth stall,application performance,bandwidth agnostic,overall performance gain,performance gain,sw prefetching
Computer science,Latency (engineering),Parallel computing,Bandwidth (signal processing),Software prefetching,Throughput,Instruction prefetch,Multi-core processor,Embedded system
Conference
Volume
ISSN
Citations 
6852
0302-9743
0
PageRank 
References 
Authors
0.34
20
3
Name
Order
Citations
PageRank
Sai Prashanth Muralidhara11998.70
Mahmut T. Kandemir27371568.54
Yuanrui Zhang318015.48