Title
Performance evaluation of interthread communicationmechanisms on multicore/multithreaded architectures
Abstract
The three major solutions for increasing the nominal performance of a CPU are: multiplying the number of cores per socket, expanding the embedded cache memories and use multi-threading to reduce the impact of the deep memory hierarchy. Systems with tens or hundreds of hardware threads, all sharing a cache coherent UMA or NUMA memory space, are today the de-facto standard. While these solutions can easily provide benefits in a multi-program environment, they require recoding of applications to leverage the available parallelism. Threads must synchronize and exchange data, and the overall performance is heavily in influenced by the overhead added by these mechanisms, especially as developers try to exploit finer grain parallelism to be able to use all available resources.
Year
DOI
Venue
2012
10.1145/2287076.2287098
HPDC
Keywords
Field
DocType
nominal performance,finer grain parallelism,de-facto standard,overall performance,multithreaded architecture,embedded cache memory,available parallelism,available resource,interthread communicationmechanisms,deep memory hierarchy,numa memory space,performance evaluation,cache coherent uma,lock,performance,cache memory,cache coherence,queue
Uniform memory access,Cache pollution,CPU cache,Cache,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Page cache,Non-uniform memory access,Cache coloring,Distributed computing
Conference
Citations 
PageRank 
References 
6
0.57
3
Authors
5
Name
Order
Citations
PageRank
Davide Pasetto116311.77
Massimiliano Meneghin21257.21
Hubertus Franke31257104.86
Fabrizio Petrini42050165.82
Jimi Xenidis528122.90