Name
Abstract | ||
|---|---|---|
This paper presents a hardware implementation of an improved version of an encryption algorithm, namely the Data Encryption Standard. This modification realizes an enhancement, which is much more secure due to an enlarged key length of 768 bits. Upward compatibility is ensured so that the use of the chip for standard DES encryption is still possible. All four standard encryption modes (ECB, CBC, CFB, OFB) are included in the implementation. A standard interface allows a flexible use in different environments. The encryption kernel of the chip achieves a ciphering rate of more than 40 Mbit/s, which is only reduced by the chosen, fully asynchronous handshake protocol to about 10 Mbit/s. The chip has been fabricated and successfully tested. |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1016/0165-6074(90)90218-X | Microprocessing and Microprogramming |
DocType | Volume | Issue |
Journal | 30 | 1 |
ISSN | Citations | PageRank |
0165-6074 | 0 | 0.34 |
References | Authors | |
2 | 4 | |