Name
Abstract | ||
|---|---|---|
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the heat generated, and the performance impact of dealing with thermal emergencies. So far microarchitectural techniques to control temperature have mainly focused on the processor backend (in particular the execution units), whereas the frontend has not received much attention. However, as the temperature of the backend remains controlled and the processor throughput increases, the heat dissipated by the frontend becomes more significant, and one of the major contributors to the total average temperature. This paper proposes and evaluates a distributed frontend for clustered microarchitectures that is able to reduce power density and temperature. First, a distributed mechanism for renaming and committing instructions is proposed. Second, a sub-banked trace cache with a bank hopping mechanism is presented. Finally, a method to improve the sub-banking is proposed based on a biased mapping function to distribute bank accesses to balance temperature. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/HPCA.2005.12 | HPCA |
Keywords | Field | DocType |
execution unit,peak temperature,processor throughput increase,temperature reduction,on-chip average,bank access,total average temperature,processor design,processor backend,major contributor,power density,temperature control,chip | Bottleneck,Computer science,Parallel computing,Temperature control,Real-time computing,Power density,Processor design,Throughput,Trace Cache,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-0897 | 0-7695-2275-0 | 25 |
PageRank | References | Authors |
2.17 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pedro Chaparro | 1 | 248 | 17.27 |
| Grigorios Magklis | 2 | 702 | 45.64 |
| Jose Gonzalez | 3 | 90 | 7.98 |
| Antonio González | 4 | 3178 | 229.66 |