Paper Info
Title
An efficient and low power architecture design for motion estimation using global elimination algorithm
Abstract
This paper presents a new algorithm and architecture for motion estimation. The proposed global elimination algorithm (GEA) is derived from successive elimination algorithm (SEA). The main idea is to remove the branches of SEA to make data flow more regular and suitable for hardware. Besides, the processing time per motion vector for GEA is fixed, no initial guess is required, and the skipping ratio of search positions can be fixed within frames and is even higher than 99%. The average PSNR of compensated frames is almost the same (within 0.1 dB) as that of full-search block matching algorithm (FBMA). An architecture composed of a systolic part, an adder tree, and a comparator tree is also developed for GEA. Simulation results show our design outperforms many FBMA architectures in normalized processing capability per gate and normalized power at gate level.
Year
DOI
Venue
2002
10.1109/ICASSP.2002.5745310
ICASSP
Keywords
Field
DocType
logic gates,data flow,psnr,motion estimation,process capability,digital signal processing,algorithm design and analysis,computer architecture,hardware
Digital signal processing,Block-matching algorithm,Algorithm design,Comparator,Adder,Computer science,Algorithm,Motion estimation,Data flow diagram,Motion vector
Conference
Volume
ISSN
ISBN
3
1520-6149
0-7803-7402-9
Citations 
PageRank 
References 
11
1.55
7
Authors
4
Name
Order
Citations
PageRank
Yu-Wen Huang11116114.02
Shao-Yi Chien21603154.48
Bing-Yu Hsieh348354.76
Liang-Gee Chen43637383.22