Name
Abstract | ||
|---|---|---|
Reuse-based intellectual property (IP) design is one of the most promising techniques to take the SoC design quickly into market. To facilitate better IP reuse, it is desirable to have IP exchanged in the software form such as hardware description language (HDL) source codes. However, soft IP has higher protection requirements than hard IP, and most existing hard IP protection techniques are not applicable to soft IP. Here, we propose two practical schemes for HDL code protection by inherent characteristic of the FPGA, including look-up table (LUT) units and distributed SRAM, which can be properly documented and synthesizable for reuse. For combinational logic system, the LUT components are very suitable for hiding watermarking by assigning some author's signature into unused logic states. For sequential logic system, we use RAM-based finite state machine (FSM) or programmable finite state machine (PSM) to embed the personal watermark. Without changing the original algorithm in the reused device and increasing extra HDL modules, the proposed watermarking technique is suitable for HDL-based reused IP protection. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/IIH-MSP.2007.326 | IIH-MSP |
Keywords | Field | DocType |
extra hdl module,sequential circuits,logic states,finite state machines,programmable finite state machine,intellectual property module protection,ip reuse,hardware description language source codes,combinational circuits,hdl-based ip module protection,code protection,soft intellectual property,hardware description languages,sequential logic system,combinational logic system,sram chips,hdl code protection,watermarking technique,hard intellectual property,system-on-chip,existing hard ip protection,industrial property,logic design,watermarking,integrated circuit design,distributed sram,ip protection,fpga,system-on-chip design,higher protection requirement,field programmable gate arrays,hard ip,look-up table units,soft ip,table lookup,reuse-based intellectual property design,finite state machine,intellectual property,look up table,hardware description language,source code,system on chip | Logic synthesis,Source code,Computer science,Watermark,Artificial intelligence,Hardware description language,Computer vision,Sequential logic,Soft IP,Field-programmable gate array,Finite-state machine,Operating system,Embedded system | Conference |
Volume | ISBN | Citations |
2 | 978-0-7695-2994-1 | 0 |
PageRank | References | Authors |
0.34 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Min-Chuan Lin | 1 | 4 | 1.95 |
| Guo-Ruey Tsai | 2 | 2 | 1.06 |
| Chun-Rong Wu | 3 | 0 | 0.34 |
| Ching-Hui Lin | 4 | 0 | 0.34 |