Name
Abstract | ||
|---|---|---|
A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and rec... |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/4.568823 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Random access memory,Circuit testing,Computer graphics,Design methodology,Character generation,Logic circuits,Image processing,Flexible printed circuits,CMOS process,Application software | Journal | 32 |
Issue | ISSN | Citations |
5 | 0018-9200 | 4 |
PageRank | References | Authors |
2.96 | 0 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Watanabe | 1 | 252 | 51.28 |
| R. Fujita | 2 | 4 | 2.96 |
| K. Yanagisawa | 3 | 4 | 2.96 |
| H. Tanaka | 4 | 4 | 2.96 |
| K. Ayukawa | 5 | 9 | 3.79 |
| M. Soga | 6 | 4 | 2.96 |
| Y. Tanaka | 7 | 4 | 3.30 |
| Y. Sugie | 8 | 4 | 2.96 |
| Y. Nakagome | 9 | 8 | 3.57 |