Name
Title | ||
|---|---|---|
Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking |
Abstract | ||
|---|---|---|
In this paper, we propose a design and implementation method for priority queuing mechanisms on FPGAs. First, we describe behavior of WFQ (weighted fair queuing) with several parameters in a model called concurrent periodic EFSMs. Then, we derive a parameter condition for the concurrent EFSMs to execute their transitions without deadlocks in the specified time period repeatedly under the specified temporal constraints, using parametric model checking technique. From the derived parameter condition, we can decide adequate parameter values satisfying the condition, considering total costs of components. Based on the proposed method, high-reliable and high-performance WFQ circuits for gigabit networks can be synthesized on FPGAs. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1007/978-3-540-45234-8_140 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
satisfiability,weighted fair queuing,parametric model | Computation tree logic,Gigabit,Parametric model,Model checking,Computer science,Queue,Deadlock,Parallel computing,Circuit design,Real-time computing,Weighted fair queueing,Distributed computing | Conference |
Volume | ISSN | Citations |
2778 | 0302-9743 | 0 |
PageRank | References | Authors |
0.34 | 5 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomoya Kitani | 1 | 114 | 12.88 |
| Yoshifumi Takamoto | 2 | 6 | 1.37 |
| Isao Naka | 3 | 0 | 0.34 |
| Keiichi Yasumoto | 4 | 670 | 110.78 |
| Akio Nakata | 5 | 106 | 10.07 |
| Teruo Higashino | 6 | 1086 | 119.60 |